1. Field of the Invention
The present invention relates to semiconductor memory elements and to manufacturing same, and, in particular, to dynamic semiconductor memory cells as are, for example, employed for DRAM memories, and to manufacturing same.
2. Description of Prior Art
Dynamic memory cells typically consist of a so-called selection or access transistor and a memory capacitor. FIGS. 4a and 4b show a schematic cross section of a technological realization of a dynamic memory cell known in the prior art having a trench capacitor and an electric equivalent circuit diagram of this memory cell. The reference numerals in both illustrations designate the individual circuit elements and the respective local association of the individual circuit elements in the memory cell integrated in a semiconductor chip.
As can be seen from FIG. 4a, dynamic memory cells, such as, for example, DRAM memory cells, comprise two main components, namely a memory capacitor 54 storing the charge and an access transistor 52 transferring the charge into and out of the memory capacitor 54. The memory capacitor 54 can be a trench capacitor etched into the semiconductor substrate.
The memory cell 50 according to the prior art, exemplarily illustrated in FIG. 4b, as is, for example, illustrated in the book “Technologie Hochintegrierter Schaltungen” (Technology of Large-Scale Integrated Circuits) by D. Widmann, H. Mader and H. Friedrich, 2nd edition, chapter 8.4.2, pp. 290–293, comprises an access transistor 52 and a trench capacitor 54. The access transistor 52 includes a gate terminal 52a, a drain terminal 52b, a source terminal 52c and a bulk terminal 52d. The trench capacitor 54 has a first terminal 54a and a second terminal 54b. The gate terminal 52a of the access transistor 52 is connected to a word line 56. The drain terminal 52b of the access transistor 52 is connected to a bit line 58. The source terminal 52c of the access transistor 52 is connected to the first terminal 54a of the trench capacitor 54, wherein the second terminal 54b of the trench capacitor 54 has the effect of a common capacitor plate.
In order to write data to the memory cell 50, a predetermined voltage is applied to the word line 56 so that the access transistor 52 connected to the word line 56 becomes conductive. Thus, the charge fed by the bit line 58 is collected in the trench capacitor 54.
When reading data, a predetermined voltage is applied to the word line 56 to connect the access transistor 52 through so that the charge stored in the trench capacitor 54 can be read out to the bit line 58.
In the following, an exemplary realization of a dynamic memory cell 50 having a trench capacitor 54, that is in particular a trench capacitor having a buried plate, in a semiconductor chip and its manufacture will be discussed referring to FIG. 4b by means of generalized and simplified expressions.
A trench 62 is, for example, formed in a p-doped single crystal silicon substrate 60 serving as the starting material by anisotropic plasma etching. Subsequently, a thin ONO dielectric layer 64 (ONO=oxide nitride oxide) is formed in the deep trench 62, wherein this dielectric layer adopts the function of the dielectric between the electrodes 54a, 54b of the plate capacitor 54. Subsequently, the trench 62 is filled with a polysilicon material or a highly doped n+-type silicon material in order to form one capacitor electrode 54a, wherein the semiconductor material surrounding the ONO dielectric layer 64 forms the second capacitor electrode 54b. 
The so-called buried plate 66 completely surrounding the trench 62 is then formed in the p-doped substrate material 60 by implantation. Above the buried plate 66, a p-type well 68 is implanted to about the depth of the oxide collar 64a, the p-type well 68 having the effect of the p-type bulk region of the access transistor 52. The bulk terminal 52d of the access transistor 52 is connected to the p-type bulk region 68.
As is illustrated in FIG. 4b, a field effect transistor 52 having a source region 52c, a drain region 52b and an n channel region defined therebetween is formed in the p-type bulk region 68 adjacent to the trench capacitor 54. The gate terminal region 52a is formed in an isolating layer 70 (SiO2) arranged above the substrate material. As is illustrated in FIG. 5b, a so-called surface strap contact 72 connecting the source region 52c of the field effect transistor 52 to the first electrode 54a of the trench capacitor 54 is also formed. In the isolating layer 70, the gate terminal (control electrode) 52a of the field effect transistor 52 is, for example, formed of a polysilicon material, wherein the gate terminal 52a is connected to the word line 56. In addition, an electrically conductive connection from the bit line 58 which, for example, consists of polyizide, wolfram or aluminum, to the drain terminal 52b of the field effect transistor 52 is formed through the isolating layer 70.
As is illustrated in FIG. 4b, the surface strap contact 72 produces a connection between a diffusion region, i.e. the n-type source region 52c of the field effect transistor 52, and the polysilicon region of the interior electrode 54a of the trench capacitor 54. This strap contact 72 which in the memory cell 50 is formed between the memory trench 62, i.e. the memory capacitor 54, and the access transistor 52, on the one hand, is a very important connecting element in memory cells, wherein, on the other hand, this connecting element is extremely sensitive to manufacture in memory cell arrangements 50 and thus is problematic for the characteristics of the memory cell.
As it is known, efforts for developing ever-smaller dynamic memory cells (DRAM cells) are a well-known goal in the field of semiconductor technology, wherein optimizing the memory cells as regards both the manufacturing cost and the cell density is strived for. Thus, the cell density on a DRAM chip and, at the same time, the performance of the memory elements has drastically increased over the last few years due to improvements in semiconductor technologies. If, however, the cell density on a DRAM chip is increased, it is, on the other hand, necessary to decrease the area of the individual cell in order to be able to maintain a sensible overall chip size.
Due to the continuing decrease of the structure size as mentioned above, problems in contacting the memory cells increasingly develop in DRAM cells, wherein an effective and area-saving contacting to the word lines and bit lines is particularly required to make a further miniaturization of memory cells possible.